Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training

Abstract

Memristive crossbar arrays have gained considerable attention from researchers to perform analog in-memory vector-matrix multiplications in machine learning accelerators with low power and constant computational time. This work introduces a comprehensive framework for co-designing the software and hardware for deep neural networks (DNN) based on memristive and memcapacitive crossbars while considering various non-idealities. The model takes into account device-level factors, including conductance variation, cycle-to-cycle variation, device-to-device variation, peripheral circuits for error/weight gradient computation, and high tolerance. The overall neural network performance is thoroughly assessed by integrating these elements into a unified DNN training process. The proposed framework is implemented using a hybrid approach with Python and PyTorch. Performance evaluation was conducted using a simplified 8-layer VGG network on a measured 128 x 128 array with weight resolution. Remarkably, the memristive and memcapacitive crossbar arrays achieved outstanding training accuracies of 90.02% and 91.03%, respectively, for the CIFAR-10 dataset. Additionally, detailed hardware estimation for both mem-elements devices is provided, enabling meaningful comparisons with prior works.