A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS

Abstract

This paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in analog front-end (AFE) and has efficient digital clock and data recovery (CDR). The AFE is implemented exclusively with inverter-based stages. It consists of a shunt feedback transimpedance amplifier followed by a continuous time linear equalizer (CTLE) and variable gain amplifier (VGA). High RF value, 400Ω , was employed to have better sensitivity at the cost of narrow bandwidth. Total AFE bandwidth is extended by 5.5X with CTLE peaking, series inductances between each AFE stage, and active inductor loads in the CTLE output and VGA stages. Quarter-rate, phase-locked loop (PLL) based digital CDR is implemented for clocking. The resolution of a digitally controlled oscillator (DCO) is optimized at 9-bit to balance jitter and hardware cost from the CDR. Multi-phase clock generation is accomplished by a delay locked loop (DLL). Fabricated in 28nm CMOS, the 42.7Gb/s optical receiver achieves an optical modulation amplitude (OMA) sensitivity of -3.6dBm at a bit error rate (BER)< 10-12 , 10MHz CDR bandwidth, and 3.4pJ/bit energy efficiency. © 2013 IEEE.