A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array

Abstract

A power and area efficient CMOS stochastic neuron for resistive computing device-based neural networks is presented. The stochastic neuron performs both quantization and activation function simultaneously by using a single dynamic comparator and allows power-hungry analog to digital and digital to analog converters to be removed at the cost of the increased computation time. A network learning method utilizing a noisy sigmoid function is also presented to minimize the computation time with little accuracy degradation. A prototype neuron chip fabricated in 0.18μm CMOS process successfully demonstrates the neuron's performance and the learning method is verified through network simulations. IEEE