A 10-bit, 50-MS/s Cyclic and SAR Combined Two-stage ADC with Gain Error Calibration

Abstract

This paper presents a two-stage analog to digital converter (ADC) combined with cyclic and successive approximation register (SAR) architectures. A correlated level sampling (CLS) technique is implemented to reduce the DC gain requirement of the op-amp from 65 dB to 35 dB. Moreover, a capacitor sharing technique is adopted to reduce the size of the op-amp load capacitors. The proposed ADC achieves both low-power consumption and a small chip area by means of the proposed structure. Furthermore, the conversion speed increases by operating both stages simultaneously. The ADC is fabricated using a 110 nm complementary metal- oxide semiconductor (CMOS), and occupies a core area of 0.247 mm2 . The signal-to-noise-and-distortion ratio is 56.4 dB with a 2.4-MHz input. It consumes 2.17-mW of power from a 1.2-V supply voltage, and achieves an 80.4 fJ/step of power efficiency.