A Low-power Extended-counting Delta-sigma ADC for CMOS Image Sensors

Abstract

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self- biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-µm CMOS image sensor process and occupies 0.0026 mm2 . It achieves 65 dB of signal noise and distortion ratio (SNDR) for a signalbandwidth of 156.25 kHz with a 20 MHz operatingclock and consumes 45 µW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.