9.9 A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode

Abstract

As SAR resolution increases, comparator power increases exponentially [1-2]. This problem should be mitigated, especially in battery-powered applications. Recent low power and noise comparators utilized dynamic pre-amplifiers [3-4] denoted as the NMOS dynamic bias with charge pump (NDBwCP) [3] and the floating inverter amplifier (FIA) [4], as shown in Fig. 9.9.1 (top). NDBwCP is a type of NMOS dynamic bias pre-amplifier, which is a self-timed operation, but its gain and noise are sensitive to common-mode voltage (VCM) variation. In contrast to the NDBwCP, the FIA incorporates both NMOS and PMOS input pairs (MN and MP) to enhance the overall transconductance, increasing the gain of the pre-amplifier. However, achieving a higher gain in the FIA requires a reset to VCM, necessitating extra bias circuits and increasing design overhead for VCM generation. Also, the pre-amplifier outputs settle slowly, and having the large gain of the pre-amplifier requires an additional delay for the outputs to be developed enough, which leads to slow decision speed. Furthermore, conventional comparators in the SAR ADCs [1-5] struggle to operate within the rail-to-rail input range, imposing constraints on the VCM of inputs and the DAC switching scheme that typically defines the capacitor DAC (CDAC) structure and size to be used. This limitation of input VCM range results in inefficient operation in scenarios where the common-mode voltage (VICM) varies for comparators during SAR conversion. This paper presents a SAR ADC with the CMOS split pre-amplifier comparator (CSPC), featuring rail-to-rail operation along with low-power and low-noise characteristics, eliminating the need for an additional bias circuit, resulting in 2.72fJ/conv and 70.6dB SNDR at 2MS/s. Furthermore, in the CDAC implementation, instead of the finger-length scaling, the grounded-finger CDAC structure is proposed to reduce the number of unit capacitors by 87.4% compared to conventional binary CDACs with an identical unit capacitor and achieve the un-calibrated 12b linearity with a small active area of 0.0372mm2. © 2024 IEEE.