Dual-Mode TFT Synaptic Array for Energy-Efficient On-Chip Training

Abstract

A dual-mode TFT synaptic array for on-chip training is proposed. The device employs an Al2O3/Si3N4/SiO2 gate-insulator stack and supports low-voltage short-term (ST) and high-voltage long-term (LT) operation within the same platform. The ST mode shows gradual conductance modulation and negligible cycling degradation, whereas the LT mode provides a wider memory window and better retention. In the proposed training scheme, the LT region performs vector-matrix multiplication with stored weights, while the ST region accumulates low-voltage updates before threshold-triggered LT transfer. Hardware-aware simulation using the measured ST/LT characteristics yields a final MNIST test accuracy of 97.39%, versus 53.67% for direct LT-only updating, with a 59.7% reduction in LT high-voltage update events. These results indicate that the proposed same-device dual-mode TFT array is promising for energy-efficient on-chip training. © 1980-2012 IEEE.