Hardware-Efficient Hierarchical Spiking Neural Architectures for Edge Applications

Abstract

As autonomous agents and edge devices increasingly require real-time interaction with dynamic environments, the limitations of traditional frame-based vision have become more apparent. Neuromorphic engineering, which leverages the asynchronous and sparse nature of event-based data, offers a compelling solution. This dissertation proposes a hardware-efficient spiking neural framework designed to bridge the gap between raw sensory input and high-level cognitive adaptation within a unified hierarchical architecture. The proposed framework follows the biological organization of the visual cortex, divided into two primary processing layers. At the lower level, we address spatial perception by developing a Spiking Cooperative Network (SCN) for real-time stereo matching. By exploiting the inherent hardware constraints and repetitive connectivity of spiking neurons, this architecture achieves high-speed disparity estimation with minimal FPGA resource overhead. At the higher level, the framework transitions toward semantic inference and adaptation via a Spiking Predictive Coding (SPC) architecture. This layer implements an error-driven on-chip learning mechanism, utilizing 2D mesh structures and optimized plastic rules to enable real-time environmental adaptation at the edge. By integrating these layers through a hardware-algorithm co-design approach, this research demonstrates an end-to-end event-driven pipeline that balances computational precision with extreme energy efficiency.