An 8-bit 600-MS/s Three-Comparator SAR ADC With MUX-delay Exclusion and LSB Averaging

Abstract

An 8-bit 600-MS/s three-comparator SAR ADC is presented that addresses the MUX-induced delay penalty associated with background comparator-swapping calibration. A MUX-delay exclusion techniques are proposed for the SAR loop, eliminating the MUX-induced overhead of the prior three-comparator SAR architecture and improving the conversion speed. Furthermore, an LSB averaging technique is introduced that reuses calibration data to reduce comparator noise and to mitigate the input parasitic capacitance of the three-comparator structure without additional decisions or sizing overhead. Fabricated in a 28-nm CMOS LP process, the prototype occupies 0.0024 mm2 and consumes 1.07 mW from a 1.0-V supply. Measurement results show an SNDR of 44.67 dB and an SFDR of 59.58 dB, achieving a Walden FoM of 12.8 fJ/conversion-step. © 2013 IEEE.