A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET

Abstract

High-speed time-interleaved ADCs are becoming more common in wireline receiver front-ends due to the enabling of subsequent digital processing for equalization and easier support of higher-order modulation schemes [1]. As technology nodes scale, ADCs based on the digital-intensive SAR architecture are more pervasive. However, implementations with the most common SAR algorithm that has sequential single-bit conversion cycles can result in large time-interleaving factors. Also, the sampling of wideband analog signals associated with higher data rates is difficult for conventional bootstrapped switch (BS) T/H circuits that have not adequately scaled in performance. One reason for this is that the low-duty-cycle sampling clocks, which are utilized for avoiding sampling crosstalk between time-interleaved sub-ADCs, shorten the tracking time and requires improvements in T/H circuit startup time. This motivates the use of simple NMOS switches in high-speed ADCs [2], [3]. However, this can negatively impact the high-speed linearity and ADC front-end bandwidth and also require higher supply voltages. This paper presents an ADC that utilizes both a high-bandwidth interleaver architecture based on a speed-enhanced bootstrapped switch and a pipelined-SAR unit ADC with output level shifting (OLS) settling [4] to enable low-power high-speed operation. At 38GS/s, the 7b ADC achieves 41.9fJ/conv.-step at low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB bandwidth. © 2022 IEEE.