First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency

Abstract

We propose for the first time a novel 3D AND-type flash memory array for a fully-parallel convolution block (FPCB) designed to realize compute-in-memory technology. By leveraging the structural advantages of 3D AND-type cells, the FPCB achieves area- and energy-efficient convolution and fully-connected operations with full memory utilization. In the convolution operation, the FPCB significantly reduces the number of cells and line resistance by a factor of about 10-4 or less (for the ImageNet dataset). Compared to conventional crossbars, the FPCB reduces ~96% and ~74% of area occupancy and energy consumption, respectively. © 2023 IEEE.