FPIA: Field-Programmable Ising Arrays with In-Memory Computing

Abstract

Ising Machines, a promising approach for solving combinatorial optimization problems, are naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A naïve in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. This approach, however, uses resources inefficiently due to the inherent sparsity of practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. This technique, however, requires interconnecting sub-arrays, which incurs overhead. In response, we present FPIA, an in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays. We adapt open-source tools to optimize problem embedding and model overhead. Modeling results of benchmark problems for the developed architecture show up to 10x increase in density and speed compared to the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.