Stress Simulation Module Integration into In-House Process Emulation and Application to CFET Devices

Abstract

For a long time, the performance improvement of semiconductor devices has been driven primarily by physical scaling. However, as scaling approaches its fundamental limits, stress engineering has emerged as an important technique for enhancing channel mobility. In par- ticular, gate-all-around (GAA) and complementary FET (CFET) structures are based on the (100) surface orientation, which leads to a large mobility difference between electrons and holes. As a result, stress engineering has once again become critical. In this thesis, a mechanical stress calculation module was integrated into an existing process emulation environment. By discretizing the equilibrium equations using the finite element method, a simulation framework was developed to calculate stress variations at each process step. Based on this framework, the stress distributions of two backside power- delivery architectures—buried power rail (BPR) and direct backside contact (DBC)—were compared for a GAA inverter. Key processes that directly influence channel stress, such as S/D epitaxy and SiGe release, were analyzed, and in particular, the impact of the Si bulk release process—essential for implementing DBC—was investigated. For the CFET inverter, the stress distribution throughout the entire process flow was calculated. The impact of defects that may occur during PMOS S/D formation on channel stress was evaluated, and it was confirmed that vertical defects induce tensile stress in the channel. Based on this insight, an unmerged SiGe S/D structure was applied to the upper- tier NMOS of the CFET, leveraging this characteristic. The stress variations introduced by adopting a wrap-around contact (WAC) were also analyzed.