A Low Power 10-bit 20MS/s Hybrid Flash-SAR ADC

Abstract

This paper proposes A Low Power 10-bit 20MS/s Hybrid Flash-SAR (Successive-Approximation Register) ADC (Analog-to-Digital Converter). With the advance of CMOS (Complementary Metal-Oxide-Semiconductor) process technology, the operation speed and area efficiency of transistors have increased by the decreasing channel length. However, it has become difficult to design a high gain amplifier because the gain of amplifier is proportional to the channel length. The gain of amplifier in ADC is an important factor in determining the accuracy that is proportional to the gain. While ADC using an amplifier consumes a high power, SAR ADC that do not use an amplifier is possible to be implemented by a low power. Reducing the MSB (Most Significant Bit) capacitor is a major issue because SAR ADC consumes a lot of switching energy in MSB switching operation and requires large MSB capacitors which consume large chip size. To resolve these problems, this paper uses hybrid structure. The coarse conversion which is flash ADC removes large MSB capacitors, addressing previous problems. This hybrid ADC has been designed with 0.18 um CMOS process by MagnaChip, and simulation performed by Cadence Virtuoso Spectre and Matlab.