Silicon Thin-Film Light Trapping Structure by Wafer-Scale CMOS-Compatible Process

Abstract

Silicon thin-films play an important role in various applications such as solar photovoltaics, photodetectors, and sensors. However, owing to the low coefficients of absorption in silicon, light trapping is essential for a silicon film that is a few microns thick. In this study, a silicon thin-film (less than 2 μm) light-trapping structure is designed and demonstrated using a wafer-scale complementary metal oxide semiconductor (CMOS) compatible process. The structure has four layers of nano-disks stacked on 1-μm planar crystalline silicon. The diameters of the nano-disks increase linearly from top to bottom. In the finite-difference time-domain simulation, the structure exhibits high values of absorption in the visible and near-infrared wavelength range (400–900 nm), and an absorption average higher than 90%, comparable to the Yablonovitch limit. The structure is fabricated using a spacer lithography process on an 8-inch silicon-on-insulator wafer. Reflection of the patterned area is significantly suppressed compared with a planar surface. From the simulated and experimental results (1-R average: 88%), a high absorption average value can be expected, indicating the significant potential of the designed structure when a metal reflector is attached and a relevant active device is realized.