Development of Ternary Logic Devices and their Applications to Integrated Circuit

Abstract

New computing devices and system architectures have been investigated to overcome the limitation of scaling in conventional semiconductor technology. Multi-valued logic architecture is considered as one of the key technology to reduce power consumption by decreasing the number of devices and interconnects. Several approaches to implement the ternary logic systems on post-silicon technology have been reported, but they still have critical challenges to conduct the ternary computing architecture such as complex and unfeasible fabrication technologies, and extreme operating conditions. Therefore, the development of the novel ternary logic devices and system are necessary. In this study, two types of ternary logic devices have been demonstrated, and the performances of their circuit applications were investigated; dual-channel ternary graphene barrister and stack-channel ternary logic device.

Chapter 2 details the demonstration of a dual-channel ternary logic device based on the graphene barrister structure. First, the electrical characteristics and device structure of graphene barrister were optimized by understanding the Fermi level pinning related phenomenon at the interfaces of graphene/semiconductor and graphene /dielectric. At the graphene/dielectric interface, the chemically induced Fermi level pinning like behavior was observed due to the oxygen exchange reaction between graphene and dielectric, especially in HfO2. Next, localized non-uniform Fermi level modulation at the graphene/semiconductor interface was investigated. Since the edge of graphene generate the chemical bonds with the ZnO layer, which causes the Fermi level pinning sites, the edge-free contact structure at the interface between graphene and semiconductor was suggested to achieve the uniform and enhanced electrical characteristics.

The influence of graphene doping effects on electronic devices was also investigated. The Fermi level of graphene could be controlled by changing the doping type of polymer solution and its concentration, then complementary ternary graphene field-effect transistors with the controllable intermediate state were demonstrated. Furthermore, in the graphene barrister structure, the threshold voltage was adjusted by modulating the Schottky barrier height between graphene and semiconductor using p-type and n-type dopant.

Combining these results, dual-channel ternary graphene barrister was demonstrated by parallel connecting two graphene barristors having different Schottky barrier height. Three discrete current states were observed in transfer characteristics due to the different threshold voltages of chemically doped graphene barristors. Moreover, based on the SPICE simulation using performance projected ternary barrister model, the drastic reduction in the device count by 1/20 and power consumption by 1/2000 were expected in ternary comparator configuration.

Chapter 3 details the analysis of the stack-channel ternary device based on the two ultra-thin ZnO layers and an organic separation layer. Based on the experimental results, the role of each ZnO layers in the ternary logic device was investigated. Different carrier concentration for 1st layer ZnO affects the current level of the intermediate state, and the voltage range for the intermediate state was controlled depending on the different threshold voltage of 2nd layer ZnO layer. The possibility of ternary logic circuit application was also examined by n-type resistive-load standard ternary inverter, and the power consumption, gain, and noise margin could be improved by controlling the intermediate state. Finally, the capacitance-based ternary full adder, which uses two types of capacitors and three types of standard ternary inverters, was simulated based on the experimental results of the stack-channel ternary logic device.