A 12-bit 40-MS/s SAR ADC with Calibration-less Switched Capacitive Reference Driver

Abstract

This dissertation presents a switched capacitive reference driver (SCRD) with a low energy switching scheme. In order to reduce the performance degradation from a signal-dependent voltage drop of a capacitive reference driver (CRD) without increasing the capacitance (CREF ) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles. In MSB conversion cycles, a supply voltage is used as a reference voltage to save on area and power consumption. Hence, the proposed SCRD significantly relaxes the required CREF and does not necessitate bit weight calibration or compensation requiring an auxiliary capacitor-based digital-to-analog converter (CDAC). To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about 16 dB improvement from SFDR of a SAR ADC with the CRD only. The prototype SAR ADC occupies 0.0448 mm2 and consumes 1.1 mW under a 1.2 V supply voltage, achieving gure-of-merit (FoM) of 19.59 fJ/conversion-step.