Study on the reliability characteristics methods for nanoscale device

Abstract

Recently, the semiconductor devices using various structures and materials have been studied for improving and scaling down semiconductor devices. Therefore, there is still a need for a degradation mechanism analysis and simple reliability estimation method for new devices. In this dissertation, fin field-effect transistor (FinFET), tunneling FET (TFT), and metal-insulator-metal (MIM) capacitor were used for reliability estimation, and degradation mechanisms were proposed. In chapter 1, recently developed various devices and reliability evaluation methods have been discussed extensively. In Chapter 2, the reliability of a bulk FinFET with a high-k dielectric/metal-gate stack has been investigated by comparing the effects of DC and AC stresses. We found that the relaxation in the interface traps is significantly weaker than that of bulk traps during the unipolar and bipolar AC stresses. Eventually, the interface traps became a major source of the device drift (over 60%) at the high temperature of 400 K. This finding suggests that a new strategy is required to address the PBTI reliability focusing on the residual interface states as well as the bulk trapping, particularly at a high temperature. In Chapter 3, the unique degradation behavior of a TFET under hot-carrier injection (HCI) stress has been investigated. However, while the source side (p+/p junction) of degradation (due to HCI stress) has been extensively studied, the drain side (p/n+ junction) has not been investigated yet. Our study revealed that both bulk oxide and interfacial layer degradation occurred at the drain side, while an interfacial layer degradation was dominant at the source side at 300 K. In Chapter 4, this study investigated the unique reliability characteristics of tunneling field effect transistors (TFETs) by comparing the effects of positive bias temperature instability (PBTI) and hot carrier injection (HCI) stresses. In case of hot carrier injection (HCI) stress, the interface trap generation near a p/n+ region was the primary degradation mechanism. However, strong recovery after a high-pressure hydrogen annealing and weak degradation at low temperature indicates that the degradation mechanism of TFET under the HCI stress is different from the high-energy carrier stress induced permanent defect generation mechanism observed in MOSFETs. Further study is necessary to identify the exact location and defect species causing TFET degradation; however, a significant difference is evident between the dominant reliability mechanism of TFET and MOSFET. In Chapter 5, we propose a simple method to monitor the quality of MIM capacitor. The differences in the slope of C-F curve at low and high frequency are found to be a good indicator showing the difference in the reliability characteristics of MIM capacitor. Asymmetric interface trap generation near top or bottom electrode could be monitored and clear difference was observed at various dielectric thickness, measurement temperature and stack structures.