Study of Electrical Properties of Sub-Micrometer-Scale Suspended CVD Graphene

Abstract

In this paper, the suspended graphene FET fabrication method is addressed. The electrical properties of suspended graphene FET are compared to its non-suspended counter-part after the fabrication. The silicon-based substrate is known to degrade the electrical transport quality of graphene. Due to its surface inhomogeneity which induces electron charge puddles via potential variation. However, if the graphene is suspended such substrate effects can be minimized. In order to make the suspended structure, three different types of fabrication methods were tested. After the suspended graphene FETs were successfully built, the electrical properties were measured. The field-effect mobility was obtained from the fitting by Idrain - Vgate measurement. As a results, the mobility was increased from 550 cm2V-1s-1 to 17,000 cm2V-1s-1 under hole dominant region (V < Vdirac). And from 2,800 cm^2 V^(-1) s^(-1) to 4,000 cm2V-1s-1 under electron dominant region (V > Vdirac). The yield of fabricated suspended devices with proposed technique was over 40% which is, by far, superior to any other techniques proposed so far.