On-chip spur and phase noise reduction techniques for clock generation in IoT applications

Abstract

This dissertation presents on-chip spur and phase noise reduction techniques for clock generation in IoT applications and is divided into two topics. In the first part, a spur reduction technique in fractional-N PLLs (FNPLLs) based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45° offset in each quadrant, and this nonlinear property leads to fractional spurs. The proposed 45° phase rotator with digital compensation reduces the fractional spur by 18.57dB at most, and average improvement of fractional tones is 7.89dB in 2MHz frequency step measurement. In addition, the second part covers an inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μW. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μm CMOS process. Therefore, the proposed techniques have advantages as clock generation blocks for IoT electronic devices.