Graphene-Organic hybrid device engineering for implementation of p-type ternary device

Abstract

As the world moves into the IoT era, power consumption has begun to increase in astronomical units since the number of smart devices has soared. It is one of the issues that the researchers are facing and here, multi-value logic provides one of the breakthroughs for this problem. Among the multi-value logic, ternary logic has been reported for the cost-efficient circuit design. Furthermore, implementation with ternary devices can reduce the number of devices and the complexity of circuits more efficiently. Various studies have been conducted to implement the ternary device, and the results show that the ternary barristor based on a graphene barristor operates with a high on-off ratio and a stable intermediate state. However, due to an unstable characteristic of p-type semiconductors, most of which are organic semiconductors, research on p-type ternary devices is still insufficient. In this work, the concept of p-type ternary device using p-type semiconductor is first demonstrated by device structure engineering of graphene/DNTT(dinaphtho-[2,3-b:20,30-f]thieno[3,2]-bthiophene) barristor. Charge injection layers (PEI, PAA) were inserted to control the threshold voltage of the device, and oxide layers were inserted to limit the current level. The results show the possibility of fabricating the p-type ternary device with the dual-channel ternary device and the feasibility of the circuit application.