Design of Event Detection Module with Low-power, Small-size CMOS Image Sensor with Reference Scaling

Abstract

This dissertation presents a low-power and small-size CMOS image sensor (CIS) which can be utilized as a power-efficient event detection system. Since high-resolution images are not required for most event detection purposes, power consumption and chip size of the CIS are optimized only for detection performance. The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel. The CIS chip employing a 10 μm-pitch 3T active pixel occupies a die area of 0.98 mm × 0.84 mm. The CIS dissipates 181 μW from 3.0 V analog and 1.4 V digital supplies at the maximum frame rate of 252 fps.