A 1GS/s 8-bit Loop-Unrolled SAR ADC with background offset calibration in 28nm CMOS

Abstract

The most important thing in high speed communication technology using Serializer/Deserializer is to make low power and high speed analog-to-digital converter(ADC) more than 10GS/s. But it is hard to implement more than 10GS/s with a single channel ADC. So it is implemented in a time-interleaving(TI) structure in which multiple ADCs are parallelized and operate like a single ADC. This requires a high speed single ADC to make a high speed TI ADC. To this end we designed a 1GS/s 8bit Single Channel Loop-Unrolled SAR ADC. Since the loop-unrolled SAR ADC structure contains several comparators, it is necessary to compensate the offset between comparators due to process, voltage and temperature(PVT) variations. Also in consideration of the increase in the leakage current as the micro process is developed, a method of comparator offset calibration with the single-ended calibration method is proposed.