Study on Low-Power and Low-Noise Analog Front-End Design for EEG Acquisition Applications

Abstract

This thesis describes a study on low-power and low-noise analog front-end design for EEG acquisition applications. The analog front-end design includes three neural signal amplifiers that have been designed. The designed amplifiers are analyzed and summarized. The design also introduces various low-noise and low-power circuit design techniques that are essential to design neural signal amplifier with low-noise low-power features. The proposed design introduces a micropower a capacitive-coupled chopper-stabilized amplifier with the ping-pong AZ to reduce the 1/f noise and to reduce offset. The ripple reduction loop and Gm–C low-pass filter (LPF) is implemented to reduce output ripple produced by chopper modulation. A DSL is used to provide high-pass characteristic and reduce the input offset of the amplifier. All of the capacitors used in this design, including input capacitor and variable load capacitor, are replaced with MOS-capacitors for area saving. Area of capacitor can be saved up to 90 %. A positive feedback input impedance-boosting loop (IBL) is included to increase the input impedance and CMRR. The design is fabricated using a Magnachip/SK Hynix 0.18 µm 1 poly-6 metal CMOS process and tested at a 1.5 V power supply. The proposed amplifier achieves a midband gain of 55 dB, a CMRR of 130 dB, and an input-referred noise power spectral density (PSD) of 60 nV/sqrt{Hz} at 100 Hz with a total power dissipation of 1.71 u$. The noise-efficiency-factor (NEF) of the proposed amplifier is 2.47. The chip area of the proposed amplifier is 0.29 mm^2. Also the design of two amplifiers that are previously designed is introduced. The two amplifiers are cited from published journals. Although these designs are outdated, they are also implemented with low-noise and low-power design technique, which clearly show that the proposed design showed a potential for use in bio-potential signal measurement.