Electrical Characterization and Modeling of Ternary Logic Device for Integrated Circuit

Abstract

As the number of transistors per integrated circuit (IC) significantly increases to improve the performance of system on a chip, power consumption has become the most serious problem. However, because power and speed are trade-offs in binary complementary metal–oxide–semiconductor (CMOS)-device-based ICs, it is difficult to reduce power consumption while maintaining improved performance using conventional CMOS technologies. Therefore, a new paradigm is required in order to solve the bottlenecks and reduce power consumption. Ternary logic is a kind of multi-valued logic (MVL) that is used to reduce the power consumption of ICs. Its system employs three discrete levels of signal (0, 1, 2 or -1, 0, 1). It can provide significant advantages for reducing the complexity of interconnects and the number of total transistors in ICs. Unfortunately, ternary-logic technologies have not been extensively researched, because there is no suitable ternary-logic device and no circuit-compatible compact model to make ternary-logic circuit design possible. In this dissertation, a graphene barristor (GB) and double-stacked channel structure field effect transistor (DSCFET) are proposed for implementing ternary-logic devices and circuits. In Chapter 2, GBs and their applications are discussed. A high on/off ratio of more than 103 and competitive device performance have been achieved using GBs having ZnO:N (n-type), Ge (n-type), and DNTT (n-type) at a process temperature of less than 300 °C. Based on the experimental results, a semiempirical model of GBs has been developed for evaluation of the circuit performance and for a performance projection study. Moreover, various GB-based applications have been proposed, such as a complementary inverter, tunable half-wave rectifier, and ternary full adder. In Chapter 3, a circuit-compatible model for an ultrathin oxide-semiconductor-based DSCFET and the benefit of device count reduction in DSCFET-based ternary arithmetic logic units (T-ALUs) are examined. Based on the electrical characteristics of the fabricated devices with an Al4MP/1st ZnO/Al4MP/2nd ZnO channel, a circuit-compatible SPICE model of the DSCFET was developed. Using the developed model, the voltage transfer characteristics of the standard ternary inverter (STI) were analyzed, and an optimization method was proposed to improve the performance of the STI. Furthermore, more-complex ternary-logic circuits were investigated by using a static gate design methodology for ternary logic and using the developed model. The number of transistors used in a T-ALU could be reduced by ~48% compared with a binary ALU, confirming that a ternary architecture can provide a way to detour the power consumption problem of a binary architecture.