Development of statistical compact model for graphene barristor

Abstract

Further scaling of silicon technology is getting less cost-effective and the power consumption becomes a more important factor. Thus, multi-value logic (MVL) technology is attracting attention recently. Various devices have been proposed for MVL technology, especially for ternary logic. Graphene barristor is one of the approaches configuring a ternary logic. There are two types of ternary logic performed by graphene barristor, multi-threshold voltage scheme and multi-channel doping scheme. Both methods require precise threshold voltage regulation to define an intermediate state. However, the previously reported graphene barristor models have several limitations in predicting actual device performance and could not describe the threshold voltage change by chemical doping on graphene. In this work, a graphene barristor model including the effects of charged impurity carrier and Dirac voltage shift has been developed to describe device performance more accurately. The main parameters of graphene barristor were applied statistically to the model and simulated to investigate the influence of these parameters. In addition, their implication on the ternary logic application of each main parameter has been examined.