High-order Incremental Delta-Sigma ADC for Compressive Sensing Image Sensor

Abstract

A high-order incremental delta-sigma ADC for compressive sensing image sensor is presented. This enables high-order delta-sigma ADCs to be employed in compressive sensing (CS) CMOS image sensors, despite a non-constant weight function of the ADCs. In a CS image sensor, a fixed number of pixels are selected according to a measurement matrix each time that analog-to-digital (A/D) conversion is performed, and a linear combination of the selected pixel values should be calculated and converted into a digital code. To obtain a linear combination of the pixel values, a specific sequence of the ADC input samples, which enables the ADC to generate the equally weighted sums of input samples, is derived by applying a solution to the partition problem. This ADC has been designed with 0.18 um CMOS process by Magna, and simulation is performed by Cadence Virtuoso Spectre and MATLAB.