12-bit 250 MS/s 28 mW +70 dB SFDR Non-50% RZ DAC and Modeling Random Clock Jitter Effect in NRZ and RZ DACs

Abstract

This paper presents a high-speed current-steering (CS) digital-to-analog converter (DAC) while explaining a static error and a dynamic error degrading the CS-DAC performance based on intuitive figures and theoretical equations. Moreover, the performance degradation is verified by MATLAB and Spectre Simulator. The various techniques to overcome the nonlinearity of CS-DAC are introduced in this paper referring to many other reports. Based on the various analyses and techniques for CS-DAC, a 12-bit CS-RZ DAC in 0.11 μm CMOS technology is presented for both an IQ baseband wireless transmitter (TX) and an envelope tracking (ET) signal. This DAC with DEM and RZ alleviates the current mismatch and code-dependent transients. Additionally, the non-50% duty cycle RZ mitigates a signal power loss and relaxes an image filtering requirement, compared to conventional 50% duty cycle RZ DAC. It achieves the SFDR greater than 70 dB with 0.117 mm2 of core area. The TX-DAC mode consumes a 28 mW of power and produces a 0.25 V peak-to-peak output swing. The ET-DAC mode dissipates a 40 mW of power and generates a 1 V peak-to-peak output swing. Based on this DAC with both non-return-to-zero (NRZ) and RZ mode, we analyze a random clock jitter effect for white noise jitter (WN-J) and low-pass filtered jitter (LPF-J) in NRZ and RZ DAC. From our proposed closed-form SNR equations, MATLAB simulations, and measurements, the SNR for LPF-J in RZ DAC is similar to that in NRZ DAC against the DAC designer’s expectations.