Stress Simulation of CFET Inverters with Unmerged Sige S/D and Wrap-Around Contact

Abstract

Stress profiles inside CFET inverters are analyzed with our in-house process emulator equipped with a newly developed stress module. In the conventional structure, the PMOS channel exhibits a peak compressive stress of -1.9 GPa, whereas the NMOS channel exhibits only +0.3 GPa tensile stress. In the PMOS, the horizontal defects lead to a 19 % reduction in channel stress and vertical defects induce tensile stress in the channel. Employing the unmerged SiGe S/D, the peak stress of NMOS is enhanced to + 1. 2 ~ GPa. Adopting the wrap-around contact in the PMOS lowers its channel stress by 19 % compared to the conventional contact structure. These findings offer clear guidelines for stress-engineering optimized CFET architectures. © 2025 IEEE.