Design and Analysis of a Low-Jitter High-Gain Latch-Based Time Amplifier

Abstract

This paper presents design and analysis of a latch-based time amplifier (TA). While prior studies have primarily focused on TA gain and output characteristics, this work extends the analysis to include input-referred jitter, input dynamic range, latency, and gain behavior. Analytical equations are derived to facilitate comparisons with other TA architectures, offering insights into the performance trade-off of latch-based TA. The proposed models are validated through both simulations and measurements. A prototype latch-based TA is fabricated in a 28-nm CMOS LP process to demonstrate the effectiveness of the analysis.