A Fourth-order ∆Σ Modulator Using Hybrid Noise-shaping SAR ADC with Digital Cancellation

Abstract

A hybrid delta-sigma (∆Σ) modulator is proposed to achieve additional second-order noise shaping via feedback paths consisting of the 1-bit fine quantizer output (D<inf>Fine</inf> ) and integrated residues. A 5-dB noise suppression is obtained through digital cancellation using D<inf>Fine</inf> without causing noise leakage. In a 180-nm CMOS process with a sampling rate of 12 MHz and oversampling ratios (OSRs) of 16 and 32, the ∆Σ modulator achieved signal-tonoise and distortion ratios (SNDRs) of 92.9 and 96.7 dB and power consumption of 1.3 mW from a 1.8-V supply, showing improved noise suppression and power efficiency. © 2025, Institute of Electronics Engineers of Korea. All rights reserved.