Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator

Abstract

In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multilevel-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.