Quasi-1D Model for Acceleration of Semiconductor Device Simulation Based on Compact Charge Model

Abstract

Over the past few decades, CMOS technology has advanced by scaling down semiconductor devices, improving performance, reducing power consumption, and increasing integration density. For higher performance and improved gate controllability, the device architectures have evolved from planar MOSFET to FinFET, and subsequently to GAA NSFET. To further increase integration density, next-generation semiconductor device structures such as Forksheet FET and CFET are gaining attention. However, as CMOS technology advances, semiconductor device structures are becoming increasingly complex, and the costs associated with research and development are increasing significantly. To minimize trial and error in the research and development process, the role of TCAD simulation is expected to become even more critical. However, the computational demands of TCAD simulations continue to grow along with the advancement of CMOS technology, resulting in longer simulation times. Thus, efforts to reduce the TCAD simulation time remain essential. The main reason for long simulation times in semiconductor device simulations is the bias-ramping process. Since it is difficult to generate an appropriate initial guess at the target bias condition, simulations typically begin from equilibrium and gradually increase the bias. If a suitable initial guess could be provided at the target bias condition, it would be possible to conduct semiconductor device simulations without the bias-ramping process. Based on this concept, recent studies have actively explored the acceleration of semiconductor device simulations using artificial neural networks. Using pre-trained neural networks, initial guesses can be provided to accelerate the device simulations. However, this approach requires a large dataset and training phase. In this dissertation, a novel method is proposed to generate initial guesses using a quasi- 1D model instead of artificial neural networks. The quasi-1D model uses a compact charge model for the two-dimensional cross-section perpendicular to the channel direction, while using a one-dimensional continuity equation along the channel direction. By employing a dimension-splitting approach, the computational burden is reduced, enabling efficient initial guess generation. From the quasi-1D model, the quasi-Fermi potential along the channel direction can be obtained, which is then used to generate an initial guess for TCAD device simulations. Chapter 3 presents the compact charge model necessary to calculate the quasi-1D model. A general derivation process for a multi-gate MOS structure with an arbitrary cross-section is introduced, and the charge-voltage characteristics obtained from the model are validated for various MOS structures. Chapter 4 demonstrates the acceleration of semiconductor device simulations for a long-channel GAA MOSFET using the compact charge model and the one-dimensional continuity equation. Chapter 5 demonstrates the acceleration of semiconductor device simulations for a CFET inverter with multiple channels by using the quasi-1D model. Quantum confinement effects and short-channel devices are considered, and a structural analysis method is introduced to apply the acceleration scheme to complex device structures. The proposed acceleration method has been numerically validated across various device structures and is expected to contribute to next-generation semiconductor research and development.