Energy- and Area-Efficient CMOS Neuron and Max Pooling Circuit for RRAM-Based CNN Accelerators

Abstract

This study proposes an energy-and area-efficient CMOS neuron and analog max pooling circuit for RRAM-based convolutional neural network (CNN) accelerators. The proposed max pooling circuit implements a 2 x 2 max pooling operation with a simple analog circuit in the current domain. The current-mode max pooling is performed before the current-to-voltage and voltage-to-digital conversions, thus reducing the number of circuits required for the conversions in the conventional CNN accelerators. Consequently, the 2 x 2 pooling circuit reduces the energy and area of the accelerator to a quarter. In addition to the max pooling circuit, the neuron circuit improves energy efficiency. The proposed neuron circuit implements the ReLU activation function along with digital conversion by modifying the operating principle of a conventional single-slope analog-to-digital converter. By implementing the ReLU function and digital conversion, the neuron achieves high energy efficiency by applying a high-speed asynchronous operation. A prototype chip, which included the neuron and current-mode max pooling circuit, was fabricated using a 130 nm standard CMOS process. The measurement results of the chip demonstrate its energy efficiency of 5.5 TOPS/W. Additionally, a simulation for image recognition demonstrates that a CNN accelerator employing the proposed neuron and max pooling circuit achieves 96.2 and 82.7% classification accuracies for the MNIST and Fashion-MNIST datasets, respectively.