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A CMOS-based Resistive Crossbar Array with Pulsed Neural Network for Deep Learning Accelerator

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Abstract
A CMOS-based resistive computing element (RCE), which can be integrated in a crossbar array, is presented. The RCE successfully solves the hardware constraints of the existing memristive devices such as dynamic ranges of conductance, I-V nonlinearity, and on/off ratio without increasing hardware complexity compared to other CMOS implementations. The RCE has been designed using a 65nm standard CMOS process and SPICE simulations have been performed to evaluate feasibility and functionality of the RCE. In addition, a pulsed neural network employing an RCE crossbar array has also been designed and simulated to verify the operation of the RCE. © 2019 IEEE.
Author(s)
Yeo, InjuneGi, Sang-GyunLee, Byung-geun
Issued Date
2019-05-19
Type
Conference Paper
URI
https://scholar.gist.ac.kr/handle/local/23029
Publisher
IEEE AICAS
Citation
1th IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2019)
Conference Place
CH
Ambassador Hotel HsinchuHsinchu
Appears in Collections:
Department of Electrical Engineering and Computer Science > 2. Conference Papers
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