Quantizer-less proportional path fractional-n digital pll with a low-power high-gain time amplifier and background multi-point spur calibration

Abstract

This paper presents a fractional-N digital PLL that adopts a conventional phase frequency detector (PFD) and a low-power high-gain (>200) time amplifier (TA) in proportional path. Since the TA has narrow input dynamic range, a 7-bit phase interpolator (PI) is used with background multi-point spur calibration. The proposed PLL achieves lower phase noise and better loop gain stability than the bang-bang PLL (BBPLL) that is same structure as the proposed PLL except bang-bang phase detector (BBPD) in proportional path. And the quantizer-less proportional path avoids limit cycle phenomenon for large bandwidths. Nonlinearity of the PI is digitally calibrated in background to reduce fractional spurs to below -50 dBc. The proposed PLL is fabricated in a 40-nm CMOS process and occupies 0.14 mm