A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

Abstract

This paper proposes a three-step bit period to minimize the waste of settling time of digital-analog converter in SAR ADC. By analyzing the wasted settling time of the digital-analog converter, the wasted settling time is reduced by 60% with just three delays. The proposed technology could increase ADC's sampling frequency or reduce the reference buffer's power. The proposed clock generator adopted a shared resistance architecture for area efficiency. The proposed 3-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081mm^2. Simulation results show that the proposed delay of budget 200Ω of the SFDR.