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An Adaptive Resolution Incremental Delta-Sigma ADC for CMOS Image Sensor

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Abstract
This paper presents an adaptive resolution EC-IADC for CMOS Image Sensor. To increase the power efficiency of EC-IADC, the operation was controlled according to light intensity by using photon conversion characteristics. The 2nd order IADC operates in a lowresolution mode when in high light conditions, and the EC-IADC operates in high-resolution mode when in low light conditions. IADC modulator used the CIFF structure and implemented an integrator with one amplifier using OTA sharing technique. For OTA, self-biased complementary folded-cascode amplifier were used. Input summing node of quantizer was implemented in two branches with the level-shifting technique to the passive adder circuit. This ADC has been designed with 0.18μm BCDMOS process by DB Hitek, and simulation verification performed by CADENCE Virtuoso Spectre circuit simulation tool and MATLAB.
Author(s)
Jebeom Kim
Issued Date
2022
Type
Thesis
URI
https://scholar.gist.ac.kr/handle/local/18862
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