Adaptive resolution Incremental Delta-Sigma ADC for hardware implemented Neural Network

Abstract

This paper presents Incremental Delta-Sigma ADC for ReRAM-based Neural Network. An ADC, which is capable of controlling resolution, was designed by understanding the characteristics of ReRAM. It has two different options, Inference mode and Training mode. In the training mode, EC-IADC operates as high-resolution ADC. Conductance should be managed precisely because this error affect to classification accuracy directly. On the other side, in the Inference mode, 2nd order IADC operates as low-resolution ADC, performing Convolution calculation for Neural Network. By reusing hardware, EC-IADC can achieve higher SQNR with similar circuit complexity. In this modulator, requirement of Amplifier is released by using Cascade of Integrator with Feedforward(CIFF) architecture. And further power and area saving is achieved by using Self-Biased Amp sharing, level-shifting signal summation at the input of quantizer. This ADC has been designed with 0.18μm BCDMOS process by DB HiTek. System simulation was verified with MATLAB. The circuit level simulation was performed with CADENCE Virtuoso Spectre tool. The SNR is 87.5dB with 64.4uW average power dissipation and 45.6dB with 31.2uW in each mode.