A Carrier-Based PWM Method using a Limited Range of Zero-Sequence Voltage for Common-Mode Voltage Reduction in Three-Level Inverter

Abstract

Recently, the usage of renewable energy has received a lot of attention because of environmental concerns and rising fuel prices. In a three-phase system such as a renewable energy generation application, the two-level inverters are widely applied as the grid-connected inverter. However, they have the disadvantage of requiring large-size filters or high switching frequency to satisfy the grid connection requirements. Compared to two-level inverters, the three-level inverter has a double voltage capacity as well as superior harmonic characteristics. Therefore, three-level inverters are replacing two-level inverters in the renewable energy field. Due to the increased rated power and switching frequency of grid-connected inverters, some issues by Common-Mode Voltage (CMV) have emerged in practice. The CMV may cause the Common-Mode Currents (CMC) to flow through the parasitic capacitor, increasing ElectroMagnetic Interference (EMI). Therefore, the reduction of CMV should be considered. Because the three-level inverter has an additional goal of neutral point voltage control, this thesis proposed a method for CMV reduction and neutral point voltage control in the three-level inverter. To derive an efficient method for CMV reduction and neutral point voltage control, the CMV elimination methods and CMV reduction methods of the three-level inverter previously studied are analyzed and performance characteristics are reviewed. With reference to previous studies, a combination of the Phase Opposition Disposition (POD) method for CMV reduction and the carrier-based Pulse Width Modulation (PWM) method for neutral point voltage control is presented. Thereafter, the magnitude of CMV can be completely restricted within one-sixth of the DC-link voltage by limiting the range of the Zero-Sequence Voltage (ZSV). In addition, the range of the ZSV is optimized in consideration of distortion of the output voltages due to the dead time or parasitic capacitance of the switches. The feasibility of the proposed strategy is verified by simulation. The results are analyzed to verify the performance in the operating conditions of the grid-connected inverter. Finally, the contribution and future challenges of the proposed method are described by analyzing performance and characteristics.