A 17.9-to-22.2 GHz Fractional-N Digital PLL with Reference Quadrupler supporting Wide Range Reference Frequency

Abstract

In this study, we present a new fractional-N ADPLL architecture designed for operation over a wide reference frequency range, suitable for on-chip implementation. This architecture significantly expands the narrow tuning range of existing reference multiplying structures. The reference quadrupler corrects the phase error using the LMS algorithm with a bang-bang PFD output without requiring an additional correction circuit. To implement a wide tuning range and high resolution, the reference quadrupler is optimized for low jitter performance through the integration of DTC, MDLL multiplication, and counter structures, ensuring stability against PVT changes. To improve fractional spur performance, high linearity DTC implementation and a multi-point nonlinear correction technique were applied. The proposed fractional-N PLL operates in the frequency range of 17.9 GHz to 22.2 GHz and supports reference frequencies of 22 MHz to 86 MHz. Fabricated using the TSMC 65nm GP RF process, the PLL achieves an RMS jitter of 146.3fs in integer mode and 191.9fs in fractional mode, with a power consumption of 25mW at a 70MHz reference frequency. The worst-case baseline spur is measured at -59.6 dBc, and the worst-case fractional spur is measured at -44.3 dBc. The figure of merit (FoM) is calculated to be -242.7 dB in integer mode and -240.4 dB in fractional mode. The total chip area is 0.193mm².