Input-tracking DAC for low-power high-linearity SAR ADC

Abstract

An input-tracking DAC for successive approximation register (SAR) ADCs that allows the ADC to process only the difference between two successive samples to generate an output is presented. Exploiting the fact that ADCs deployed in baseband applications are often oversampled for anti-aliasing purposes, the input sample-to-sample variation can be predicted and bounded, resulting in significant switching-power savings and ADC linearity improvement.