A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

Abstract

In a deep submicron CMOS process, variability puts a strict requirement on noise margin in MOS current-mode logic (MCML) gates. A usual approach to achieve noise margin is to increase DC gain by sizing up differential pairs. However this results in slow output settling, which limits the maximum operating speed. Thus we propose a novel MCML latch to mitigate this trade-off by using alternating low and high gain buffer structure on a bandwidth limited node. The proposed MCML latch is designed to operate at 20 GHz clock in a 32 nm CMOS process and is compared with a conventional MCML latch to prove its superiority in terms of speed, power and reliability especially when bandwidth is limited.