Settling time optimization technique for binary-weighted digital-to-analog converter
- Author(s)
- Kim, Hyo-jong; Seo, Donghwan; Lee, Byung-geun
- Type
- Article
- Citation
- IEICE Electronics Express, v.11, no.6
- Issued Date
- 2014-03
- Abstract
- Settling behavior of the binary-weighted switched-capacitor digital-to-analog converter output is analyzed and a design method for fast settling is presented. A calibration circuit that effectively reduces settling time beyond the process limit is also proposed and verified with various simulations.
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- ISSN
- 1349-2543
- DOI
- 10.1587/elex.11.20140132
- URI
- https://scholar.gist.ac.kr/handle/local/15233
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