OAK

Settling time optimization technique for binary-weighted digital-to-analog converter

Metadata Downloads
Author(s)
Kim, Hyo-jongSeo, DonghwanLee, Byung-geun
Type
Article
Citation
IEICE Electronics Express, v.11, no.6
Issued Date
2014-03
Abstract
Settling behavior of the binary-weighted switched-capacitor digital-to-analog converter output is analyzed and a design method for fast settling is presented. A calibration circuit that effectively reduces settling time beyond the process limit is also proposed and verified with various simulations.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
ISSN
1349-2543
DOI
10.1587/elex.11.20140132
URI
https://scholar.gist.ac.kr/handle/local/15233
공개 및 라이선스
  • 공개 구분공개
파일 목록
  • 관련 파일이 존재하지 않습니다.

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.