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Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop

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Abstract
A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45° offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45° phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement. © The Institution of Engineering and Technology 2016.
Author(s)
Ko, J.Heo, M.Lee, J.Kim, C.Lee, Minjae
Issued Date
2016-11
Type
Article
DOI
10.1049/el.2016.2098
URI
https://scholar.gist.ac.kr/handle/local/14016
Publisher
Institution of Engineering and Technology
Citation
ELECTRONICS LETTERS, v.52, no.23, pp.1920 - 1922
ISSN
0013-5194
Appears in Collections:
Department of Electrical Engineering and Computer Science > 1. Journal Articles
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