A Compressive Sensing-Based CMOS Image Sensor With Second-Order Sigma Delta ADCs

Abstract

This paper presents a new analog-to-digital conversion scheme for a second-order Sigma Delta incremental analog to digital converter (ADC) that can be employed in a compressive sensing (CS)-based CMOS image sensor (CIS) as a column-parallel ADC. The conversion scheme removes image distortion from a reconstructed image by making the ADC output codes represent an average of the ADC inputs. In addition, a new multiplexing scheme implementing a compressive sensing matrix helps to reduce hardware complexity and control compression ratio without hardware modifications. A 160 x 160 pixel CS-based CIS fabricated in 0.11 mu m CIS process successfully demonstrates the proposed schemes.