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A 3.9 MW bluetooth low-energy transmitter using all-digital pll-based direct fsk modulation in 55 nm CMOS

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Author(s)
Oh, S.Kim, S.Ali, I.Nga, T.T.K.Lee, D.Pu, Y.Yoo, S.-S.Lee, MinjaeHwang, K.C.Yang, Y.Lee, K.-Y.
Type
Article
Citation
IEEE Transactions on Circuits and Systems I: Regular Papers, v.65, no.9, pp.3037 - 3048
Issued Date
2018-09
Abstract
This paper presents a low-power frequency-shift keying (FSK) transmitter (TX) with an all-digital phase locked loop (ADPLL) based on direct modulation for use in Bluetooth low energy application. A low power ADPLL with a Retimer, 2-stage time to digital converter, and gain estimation technique is proposed to achieve low-power direct FSK modulation at 1 Mbps data rate. A high-efficiency class-D power amplifier, with dual output power modes and a ramping digital filter (RDF), is proposed to reduce the spurious tones. The proposed TX is implemented on 1P6M 55-nm CMOS technology with a die size of 0.53 mm2. The phase noise is -119 dBc/Hz at a 1 MHz offset with frequency of 2.44 GHz. TX output power levels of 1.6 and 10 dBm have a power consumption of 3.9 and 18 mW, respectively. The power control ranges for the 1.6 and 10 dBm modes are 25 and 23 dB, respectively. With the RDF, when the output level is +1.6 dBm, the second, and third harmonic distortions at the TX output are -44 and -49 dBm, respectively. The proposed TX achieves an error vector magnitude of 3.48% at an output power level of +1.6 dBm. ? 2004-2012 IEEE.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
1549-8328
DOI
10.1109/TCSI.2018.2803680
URI
https://scholar.gist.ac.kr/handle/local/13113
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