A Compressive Sensing CMOS Image Sensor With Partition Sampling Technique

Abstract

A CMOS image sensor (CIS) that performs compressive sensing (CS) image encoding without compromising the operating speed and hardware complexity is presented in this article. The conversion rate and the frame rate of the sensor are increased by using a high-order sigma-delta (Sigma Delta) analog-to-digital converter (ADC) to obtain linear measurements of selected pixel values for CS encoding. Image distortion caused by the nonconstant weight function of high-order Sigma Delta ADCs is eliminated by using the proposed sampling technique. The sampling technique makes the effective weights of the inputs to the ADC equal by applying a solution for the set partition problem. In addition, unlike the existing block-based CS encoding scheme that requires complicated analog multiplexers, the proposed column-based CS encoding scheme can be implemented in a hardware-efficient column-parallel fashion, as in conventional CISs. The CIS is fabricated in a 0.11-mu m 1P4M CIS process, and the sampling technique and encoding scheme are successfully demonstrated. It achieves a readout noise of 2.63e(rms)(-) and a dynamic range of 67.96 dB with a power consumption of 56.38 mW. The resulting figure of merit is 0.375 e(-).nJ, which is the lowest among those of recently reported state-of-the-art CS-CISs.