A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme

Abstract

This paper describes a 10-bit digital-to-time converter (DTC) utilizing the glitch-free dual reset method and switchable supply regulation scheme for high linearity regardless of supply ripple noise and input signal speed. The proposed circuit is designed as a single-ended structure, and a delay control is configured as a thermometer code for high differential nonlinearity (DNL) with 32 × 32 array capacitors. The DTC is optimized with a 200MHz input signal for utilizing wide bandwidth PLLs to decrease a conversion range and keep a high resolution of a time-to-digital converter to reduce the power dissipation and quantization noise, respectively. Besides, the high linearity is guaranteed in dynamic operation, which is the worst case of DTCs’ control. The output jitter is 159.3fsrms at the maximal delay, while the DTC consumes 0.603mW with a total area of 0.0085mm2. The dynamic range is 429ps with 433fs resolution with 0.066-LSB DNL and 0.506-LSB integral nonlinearity, comparable to state-of-the-art. © 2022, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.