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Showing results 1 to 4 of 4

1 Article A 1.1ÂV 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers Ju, Hyungyu ; Lee, Minjae 2016-06
2 Article A 12-bit 40-MS/s SAR ADC with Calibration-Less Switched Capacitive Reference Driver Ju, Hyungyu ; Lee, Sewon ; Lee, Minjae 2020-11
3 Article A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit Ju, Hyungyu ; Lee, Minjae 2019-02
4 Article A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers Ju, Hyungyu ; Lee, Minjae 2020-08

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